MC9S08DZ60 Datasheet, PDF (88/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 6 Parallel Input/Output Control
6.5.1.3 Port A Pull Enable Register (PTAPE)
R
W
Reset:
7
PTAPE7
0
6
PTAPE6
5
PTAPE5
4
PTAPE4
3
PTAPE3
2
PTAPE2
1
PTAPE1
0
0
0
0
0
0
Figure 6-5. Internal Pull Enable for Port A Register (PTAPE)
Table 6-3. PTAPE Register Field Descriptions
0
PTAPE0
0
Field
Description
7:0
PTAPE[7:0]
Internal Pull Enable for Port A Bits — Each of these control bits determines if the internal pull-up or pull-down
device is enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no
effect and the internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
6.5.1.4 Port A Slew Rate Enable Register (PTASE)
R
W
Reset:
7
PTASE7
1
6
PTASE6
5
PTASE5
4
PTASE4
3
PTASE3
2
PTASE2
1
PTASE1
1
1
1
1
1
1
Figure 6-6. Slew Rate Enable for Port A Register (PTASE)
Table 6-4. PTASE Register Field Descriptions
0
PTASE0
1
Field
Description
7:0
PTASE[7:0]
Output Slew Rate Enable for Port A Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
88
PRELIMINARY
Freescale Semiconductor
Subject to Change