MC9S08DZ60 Datasheet, PDF (23/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

1 kHZ
LPO
MCGERCLK
MCGIRCLK
TPM1CLK TPM2CLK
RTC
COP
TPM1
TPM2
IIC
MCG
MCGFFCLK
÷2
FFCLK*
Chapter 1 Device Overview
SCI1
SCI2
SPI
MCGOUT
MCGLCLK
÷2 ^BUSCLK
XOSC
CPU
BDC
ADC
MSCAN FLASH EEPROM
EXTAL XTAL
* The fixed frequency clock (FFCLK) is internally
synchronized to the bus clock and must not exceed one half
of the bus clock frequency.
ADC has min and max
frequency requirements.
See the ADC chapter
and electricals appendix
for details.
Figure 1-2. MC9S08DZ60 System Clock Distribution Diagram
FLASH and EEPROM
have frequency
requirements for program
and erase operation. See
the electricals appendix
for details.
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
Freescale Semiconductor
PRELIMINARY
23
Subject to Change