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MC9S08DZ60 Datasheet, PDF (3/396 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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MC9S08DZ60 Series Features
8-Bit HCS08 Central Processor Unit (CPU)
⢠40-MHz HCS08 CPU (20-MHz bus)
⢠HC08 instruction set with added BGND instruction
⢠Support for up to 32 interrupt/reset sources
On-Chip Memory
⢠FLASH read/program/erase over full operating voltage
and temperature
â MC9S08DZ60 = 60K
â MC9S08DZ48 = 48K
â MC9S08DZ32 = 32K
â MC9S08DZ16 = 16K
⢠Up to 2K EEPROM in-circuit programmable memory;
8-byte single-page or 4-byte dual-page erase sector;
Program and Erase while executing FLASH; Erase abort
⢠Up to 4K random-access memory (RAM)
Power-Saving Modes
⢠Two very low power stop modes
⢠Reduced power wait mode
⢠Very low power real time interrupt for use in run, wait,
and stop
Clock Source Options
⢠Oscillator (XOSC) â Loop-control Pierce oscillator;
Crystal or ceramic resonator range of 31.25 kHz to
38.4 kHz or 1 MHz to 16 MHz
⢠Multi-purpose Clock Generator (MCG) â PLL and
FLL modes; Internal reference clock with trim
adjustment; External reference with oscillator/resonator
options
System Protection
⢠Watchdog computer operating properly (COP) reset
with option to run from backup dedicated 1-kHz internal
clock source or bus clock
⢠Low-voltage detection with reset or interrupt; selectable
trip points
⢠Illegal opcode detection with reset
⢠Illegal address detection with reset
⢠FLASH block protect
⢠Loss-of-lock protection
Development Support
⢠Single-wire background debug interface
⢠On-chip, in-circuit emulation (ICE) with real-time bus
capture
Peripherals
⢠ADC â 24-channel, 10-bit resolution, 2.5 µs
conversion time, automatic compare function,
1.7 mV/°C temperature sensor, internal bandgap
reference channel
⢠ACMPx â Two analog comparators with selectable
interrupt on rising, falling, or either edge of comparator
output; compare option to ï¬xed internal bandgap
reference voltage
⢠MSCAN â CAN protocol - Version 2.0 A, B; standard
and extended data frames; Support for remote frames;
Five receive buffers with FIFO storage scheme; Flexible
identiï¬er acceptance ï¬lters programmable as: 2 x 32-bit,
4 x 16-bit, or 8 x 8-bit
⢠SCIx â Two SCIs supporting LIN 2.0 Protocol and
SAE J2602 protocols; Full duplex non-return to zero
(NRZ); Master extended break generation; Slave
extended break detection; Wakeup on active edge
⢠SPI â Full-duplex or single-wire bidirectional;
Double-buffered transmit and receive; Master or Slave
mode; MSB-ï¬rst or LSB-ï¬rst shifting
⢠IIC â Up to 100 kbps with maximum bus loading;
Multi-master operation; Programmable slave address;
General Call Address; Interrupt driven byte-by-byte data
transfer
⢠TPMx â One 6-channel (TPM1) and one 2-channel
(TPM2); Selectable input capture, output compare, or
buffered edge-aligned PWM on each channel
⢠RTC â (Real-time counter) 8-bit modulus counter with
binary or decimal based prescaler; Real-time clock
capabilities using external crystal and RTC for precise
time base, time-of-day, calendar or task scheduling
functions; Free running on-chip low power oscillator
(1 kHz) for cyclic wake-up without external components
Input/Output
⢠53 general-purpose input/output (I/O) pins and 1
input-only pin
⢠24 interrupt pins with selectable polarity on each pin
⢠Hysteresis and conï¬gurable pull device on all input pins.
⢠Conï¬gurable slew rate and drive strength on all output
pins.
Package Options
⢠64-pin low-proï¬le quad ï¬at-pack (LQFP) â 10x10 mm
⢠64-pin quad ï¬at-pack no lead (QFN) â 9x9 mm
⢠48-pin low-proï¬le quad ï¬at-pack (LQFP) â 7x7 mm
⢠32-pin low-proï¬le quad ï¬at-pack (LQFP) â 7x7 mm
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