MC9S08DZ60 Datasheet, PDF (103/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

6.5.5.3 Port E Pull Enable Register (PTEPE)
Chapter 6 Parallel Input/Output Control
R
W
Reset:
7
PTEPE7
0
6
PTEPE6
5
PTEPE5
4
PTEPE4
3
PTEPE3
2
PTEPE2
1
PTEPE1
0
0
0
0
0
0
Figure 6-34. Internal Pull Enable for Port E Register (PTEPE)
Table 6-32. PTEPE Register Field Descriptions
0
PTEPE0
0
Field
Description
7:0
PTEPE[7:0]
Internal Pull Enable for Port E Bits — Each of these control bits determines if the internal pull-up device is
enabled for the associated PTE pin. For port E pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port E bit n.
1 Internal pull-up device enabled for port E bit n.
6.5.5.4 Port E Slew Rate Enable Register (PTESE)
7
R
PTESE7
W
6
PTESE6
5
PTESE5
4
PTESE4
3
PTESE3
2
PTESE2
1
PTESE1¹
Reset:
1
1
1
1
1
1
1
Figure 6-35. Slew Rate Enable for Port E Register (PTESE)
1 _{PTESE1 has no effect on the input-only PTE1 pin.}
0
PTESE0
1
Table 6-33. PTESE Register Field Descriptions
Field
Description
7:0
PTESE[7:0]
Output Slew Rate Enable for Port E Bits — Each of these control bits determines if the output slew rate control
is enabled for the associated PTE pin. For port E pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port E bit n.
1 Output slew rate control enabled for port E bit n.
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
Freescale Semiconductor
PRELIMINARY
103
Subject to Change