MC9S08DZ60 Datasheet, PDF (212/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Inter-Integrated Circuit (S08IICV2)
11.4.2 10-bit Address
For 10-bit addressing, 0x11110 is used for the first 5 bits of the first address byte. Various combinations of
read/write formats are possible within a transfer that includes 10-bit addressing.
11.4.2.1 Master-Transmitter Addresses a Slave-Receiver
The transfer direction is not changed (see Table 11-8). When a 10-bit address follows a START condition,
each slave compares the first seven bits of the first byte of the slave address (11110XX) with its own
address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that more than one device
will find a match and generate an acknowledge (A1). Each slave that finds a match will compare the eight
bits of the second byte of the slave address with its own address, but only one slave will find a match and
generate an acknowledge (A2). The matching slave will remain addressed by the master until it receives
a STOP condition (P) or a repeated START condition (Sr) followed by a different slave address.
Slave Address 1st 7 bits R/W
Slave Address 2nd byte
S _{11110 + AD10 + AD9}
0 ^A1
AD[8:1]
A2 Data A ... Data A/A P
Table 11-8. Master-Transmitter Addresses Slave-Receiver with a 10-bit Address
11.4.2.2 Master-Receiver Addresses a Slave-Transmitter
The transfer direction is changed after the second R/W bit (see Table 11-9). Up to and including
acknowledge bit A2, the procedure is the same as that described for a master-transmitter addressing a
slave-receiver. After the repeated START condition (Sr), a matching slave remembers that it was addressed
before. This slave then checks whether the first seven bits of the first byte of the slave address following
Sr are the same as they were after the START condition (S), and tests whether the eighth (R/W) bit is 1. If
there is a match, the slave considers that it has been addressed as a transmitter and generates acknowledge
A3. The slave-transmitter remains addressed until it receives a STOP condition (P) or a repeated START
condition (Sr) followed by a different slave address.
After a repeated START condition (Sr), all other slave devices will also compare the first seven bits of the
first byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of
them will be addressed because R/W = 1 (for 10-bit devices), or the 11110XX slave address (for 7-bit
devices) does not match.
Slave Address
R/W
Slave Address
Slave Address R/W
S
1st 7 bits
A1
2nd byte
A2 Sr
1st 7 bits
A3 Data A ... Data A P
11110 + AD10 + AD9 0
AD[8:1]
11110 + AD10 + AD9 1
Table 11-9. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address
11.4.3 General Call Address
General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches
the general call address as well as its own slave address. When the IIC responds to a general call, it acts as
a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after
the first byte transfer to determine whether the address matches is its own slave address or a general call.
If the value is “00”, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied
from a general call address by not issuing an acknowledgement.
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
212
PRELIMINARY
Freescale Semiconductor
Subject to Change