MC9S08DZ60 Datasheet, PDF (109/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

6.5.7.3 Port G Pull Enable Register (PTGPE)
Chapter 6 Parallel Input/Output Control
7
R
0
W
6
5
4
3
2
1
0
0
PTGPE5
PTGPE4
PTGPE3
PTGPE2
PTGPE1
PTGPE0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 6-44. Internal Pull Enable for Port G Register (PTGPE)
Table 6-42. PTGPE Register Field Descriptions
Field
Description
5:0
Internal Pull Enable for Port G Bits — Each of these control bits determines if the internal pull-up device is
PTGPE[5:0] enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pull devices are disabled.
0 Internal pull-up device disabled for port G bit n.
1 Internal pull-up device enabled for port G bit n.
6.5.7.4 Port G Slew Rate Enable Register (PTGSE)
7
R
0
W
6
5
4
3
2
1
0
0
PTGSE5
PTGSE4
PTGSE3
PTGSE2
PTGSE1
PTGSE0
Reset:
0
0
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 6-45. Slew Rate Enable for Port G Register (PTGSE)
Table 6-43. PTGSE Register Field Descriptions
Field
Description
5:0
Output Slew Rate Enable for Port G Bits — Each of these control bits determines if the output slew rate control
PTGSE[5:0] is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
Freescale Semiconductor
PRELIMINARY
109
Subject to Change