MC9S08DZ60 Datasheet, PDF (223/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Freescale’s Controller Area Network (S08MSCANV1)
Table 12-2. CANCTL1 Register Field Descriptions (continued)
Field
2
WUPM
1
SLPAK
0
INITAK
Description
Wake-Up Mode — If WUPE in CANCTL0 is enabled, this bit defines whether the integrated low-pass filter is
applied to protect the MSCAN from spurious wake-up (see Section 12.5.5.4, “MSCAN Sleep Mode”).
0 MSCAN wakes up on any dominant level on the CAN bus
1 MSCAN wakes up only in case of a dominant pulse on the CAN bus that has a length of T_wup
Sleep Mode Acknowledge — This flag indicates whether the MSCAN module has entered sleep mode (see
Section 12.5.5.4, “MSCAN Sleep Mode”). It is used as a handshake flag for the SLPRQ sleep mode request.
Sleep mode is active when SLPRQ = 1 and SLPAK = 1. Depending on the setting of WUPE, the MSCAN will
clear the flag if it detects activity on the CAN bus while in sleep mode.CPU clearing the SLPRQ bit will also reset
the SLPAK bit.
0 Running — The MSCAN operates normally
1 Sleep mode active — The MSCAN has entered sleep mode
Initialization Mode Acknowledge — This flag indicates whether the MSCAN module is in initialization mode
(see Section 12.5.5.5, “MSCAN Initialization Mode”). It is used as a handshake flag for the INITRQ initialization
mode request. Initialization mode is active when INITRQ = 1 and INITAK = 1. The registers CANCTL1,
CANBTR0, CANBTR1, CANIDAC, CANIDAR0–CANIDAR7, and CANIDMR0–CANIDMR7 can be written only by
the CPU when the MSCAN is in initialization mode.
0 Running — The MSCAN operates normally
1 Initialization mode active — The MSCAN is in initialization mode
12.3.3 MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
R
W
Reset:
7
SJW1
0
6
SJW0
5
BRP5
4
BRP4
3
BRP3
2
BRP2
0
0
0
0
0
Figure 12-6. MSCAN Bus Timing Register 0 (CANBTR0)
1
BRP1
0
0
BRP0
0
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-3. CANBTR0 Register Field Descriptions
Field
Description
7:6
SJW[1:0]
5:0
BRP[5:0]
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see Table 12-4).
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see Table 12-5).
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
Freescale Semiconductor
PRELIMINARY
223
Subject to Change