MC9S08DZ60 Datasheet, PDF (374/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.12.1 Control Timing
Table A-13. Control Timing
Num C
Rating
Symbol
Min
Typical Max Unit
1
Bus frequency (t_cyc = 1/f_Bus)
f_Bus
dc
—
20
MHz
2
Internal low-power oscillator period
t_LPO
700
1300 µs
3
External reset pulse width¹
t_extrst
1.5 x
f_{Self_reset}
—
ns
4
Reset low drive²
t_rstdrv
34 x
f_{Self_reset}
—
ns
5
Active background debug mode latch setup time
t_MSSU
25
—
ns
6
Active background debug mode latch hold time
t_MSH
25
—
ns
IRQ/PIAx/ PIBx/PIDx pulse width
7
Asynchronous path²
Synchronous path³
Port rise and fall time (load = 50 pF)³
8
Slew rate control disabled
Slew rate control enabled
t_ILIH, t_IHIL
100
—
1.5 t_cyc
t_Rise, t_Fall
—
3
—
30
—
ns
ns
1 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
2 _{When any reset is initiated, internal circuitry drives the reset pin low for about 34 cycles of fSelf_reset and then samples the}
level on the reset pin about 38 cycles later to distinguish external reset requests from internal requests.
3 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.}
RESET PIN
t_extrst
Figure A-10. Reset Timing
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
374
PRELIMINARY
Freescale Semiconductor
Subject to Change