MC9S08DZ60 Datasheet, PDF (146/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Purpose Clock Generator (S08MCGV1)
In bypassed low power external mode, the MCGOUT clock is derived from the external reference clock.
The external reference clock which is enabled can be an external crystal/resonator or it can be another
external clock source.
The PLL and the FLL are disabled in low power states and the MCGLCLK will not be available for BDC
communications. If the BDM becomes active the mode will switch to one of the bypassed external modes
as determined by the state of the PLLS bit.
8.4.1.9 Stop
Stop mode is entered whenever the MCU enters a STOP state. In this mode, the FLL and PLL are disabled
and all MCG clock signals are static except in the following cases:
MCGIRCLK will be active in stop mode when all the following conditions occur:
• IRCLKEN = 1
• IREFSTEN = 1
MCGERCLK will be active in stop mode when all the following conditions occur:
• ERCLKEN = 1
• EREFSTEN = 1
8.4.2 Mode Switching
When switching between engaged internal and engaged external modes the IREFS bit can be changed at
anytime, but the RDIV bits must be changed simultaneously so that the reference frequency stays in the
range required by the state of the PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected, or 1 MHz to
2 MHz if the PLL is selected). After a change in the IREFS value the FLL or PLL will begin locking again
after the switch is completed. The completion of the switch is shown by the IREFST bit.
The CLKS bits can also be changed at anytime, but in order for the MCGLCLK to be configured correctly
the RDIV bits must be changed simultaneously so that the reference frequency stays in the range required
by the state of the PLLS bit (31.25 kHz to 39.0625 kHz if the FLL is selected, or 1 MHz to 2MHz if the
PLL is selected). The actual switch to the newly selected clock will be shown by the CLKST bits. If the
newly selected clock is not available, the previous clock will remain selected.
For details see Figure 8-8.
8.4.3 Bus Frequency Divider
The BDIV bits can be changed at anytime and the actual switch to the new frequency will occur
immediately.
8.4.4 Low Power Bit Usage
The low power bit (LP) is provided to allow the FLL or PLL to be disabled and thus conserve power when
these systems are not being used. However, in some applications it may be desirable to enable the FLL or
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
146
PRELIMINARY
Freescale Semiconductor
Subject to Change