MC9S08DZ60 Datasheet, PDF (147/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Purpose Clock Generator (S08MCGV1)
PLL and allow it to lock for maximum accuracy before switching to an engaged mode. Do this by writing
the LP bit to 0.
8.4.5 Internal Reference Clock
When IRCLKEN is set the internal reference clock signal will be presented as MCGIRCLK, which can be
used as an additional clock source. The MCGIRCLK frequency can be re-targeted by trimming the period
of the internal reference clock. This can be done by writing a new value to the TRIM bits in the MCGTRM
register. Writing a larger value will decrease the MCGIRCLK frequency, and writing a smaller value to
the MCGTRM register will increase the MCGIRCLK frequency. The TRIM bits will effect the MCGOUT
frequency if the MCG is in FLL engaged internal (FEI), FLL bypassed internal (FBI), or bypassed low
power internal (BLPI) mode. The TRIM and FTRIM value is initialized by POR but is not affected by other
resets.
Until MCGIRCLK is trimmed, programming low reference divider (RDIV) factors may result in
MCGOUT frequencies that exceed the maximum chip-level frequency and violate the chip-level clock
timing specifications (see the Device Overview chapter).
If IREFSTEN and IRCLKEN bits are both set, the internal reference clock will keep running during stop
mode in order to provide a fast recovery upon exiting stop.
8.4.6 External Reference Clock
The MCG module can support an external reference clock with frequencies between 31.25 kHz to 5 MHz
in all modes. When ERCLKEN is set, the external reference clock signal will be presented as
MCGERCLK, which can be used as an additional clock source. When IREFS = 1, the external reference
clock will not be used by the FLL or PLL and will only be used as MCGERCLK. In these modes, the
frequency can be equal to the maximum frequency the chip-level timing specifications will support (see
the Device Overview chapter).
If EREFSTEN and ERCLKEN bits are both set or the MCG is in FEE, FBE, PEE, PBE or BLPE mode,
the external reference clock will keep running during stop mode in order to provide a fast recovery upon
exiting stop.
If CME bit is written to 1, the clock monitor is enabled. If the external reference falls below a certain
frequency (f_{loc_high} or f_{loc_low} depending on the RANGE bit in the MCGC2), the MCU will reset. The LOC
bit in the System Reset Status (SRS) register will be set to indicate the error.
8.4.7 Fixed Frequency Clock
The MCG presents the divided reference clock as MCGFFCLK for use as an additional clock source. The
MCGFFCLK frequency must be no more than 1/4 of the MCGOUT frequency to be valid. Because of this
requirement, the MCGFFCLK is not valid in bypass modes for the following combinations of BDIV and
RDIV values:
• BDIV=00 (divide by 1), RDIV < 010
BDIV=01 (divide by 2), RDIV < 011
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
Freescale Semiconductor
PRELIMINARY
147
Subject to Change