MC9S08DZ60 Datasheet, PDF (359/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
T_J = T_A + (P_D × θ_JA)
Eqn. A-1
where:
T_A = Ambient temperature, °C
θ_JA = Package thermal resistance, junction-to-ambient, °C/W
P_D = P_int + P_I/O
P_int = I_DD × V_DD, Watts — chip internal power
P_I/O = Power dissipation on input and output pins — user determined
For most applications, P_I/O << P_int and can be neglected. An approximate relationship between P_D and T_J
(if P_I/O is neglected) is:
P_D = K ÷ (T_J + 273°C)
Solving equations 1 and 2 for K gives:
Eqn. A-2
K = P_D × (T_A + 273°C) + θ_JA × (P_D)²
Eqn. A-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring
P_D (at equilibrium) for a known T_A. Using this value of K, the values of P_D and T_J can be obtained by
solving equations 1 and 2 iteratively for any value of T_A.
A.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table A-4. ESD and Latch-up Test Conditions
Model
Human Body
Latch-up
Description
Series Resistance
Storage Capacitance
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
Symbol
R1
C
–
Value
1500
100
3
–2.5
7.5
Unit
Ω
pF
V
V
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
Freescale Semiconductor
PRELIMINARY
359
Subject to Change