MC9S08DZ60 Datasheet, PDF (224/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Freescale’s Controller Area Network (S08MSCANV1)
Table 12-4. Synchronization Jump Width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization Jump Width
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
Table 12-5. Baud Rate Prescaler
BRP5
0
0
0
0
:
1
BRP4
0
0
0
0
:
1
BRP3
0
0
0
0
:
1
BRP2
0
0
0
0
:
1
BRP1
0
0
1
1
:
1
BRP0
0
1
0
1
:
1
Prescaler value (P)
1
2
3
4
:
64
12.3.4 MSCAN Bus Timing Register 1 (CANBTR1)
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
R
W
Reset:
7
SAMP
0
6
TSEG22
5
TSEG21
4
TSEG20
3
TSEG13
2
TSEG12
1
TSEG11
0
TSEG10
0
0
0
0
0
0
0
Figure 12-7. MSCAN Bus Timing Register 1 (CANBTR1)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 12-6. CANBTR1 Register Field Descriptions
Field
7
SAMP
Description
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit¹.
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
224
PRELIMINARY
Freescale Semiconductor
Subject to Change