MC9S08DZ60 Datasheet, PDF (156/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Purpose Clock Generator (S08MCGV1)
START
IN BLPI MODE
MCGC2 = $00
OPTIONAL: _NO
CHECK LOCK
= 1?
YES
MCGC2 = $36
CHECK
NO
OSCINIT = 1 ?
YES
MCGC1 = $38
CHECK
NO
IREFST = 0?
YES
OPTIONAL: _NO
CHECK LOCK
= 1?
YES
CHECK
NO
CLKST = %00?
YES
CONTINUE
IN FEE MODE
Figure 8-11. Flowchart of BLPI to FEE Mode Transition using a 4 MHz crystal
8.5.3 Calibrating the Internal Reference Clock (IRC)
The IRC is calibrated by writing to the MCGTRM register first, then using the FTRIM bit to “fine tune”
the frequency. We will refer to this total 9-bit value as the trim value, ranging from 0x000 to 0x1FF, where
the FTRIM bit is the LSB.
The trim value after a POR is always 0x100 (MCGTRM = 0x80 and FTRIM = 0). Writing a larger value
will decrease the frequency and smaller values will increase the frequency. The trim value is linear with
the period, except that slight variations in wafer fab processing produce slight non-linearities between trim
value and period. These non-linearities are why an iterative trimming approach to search for the best trim
value is recommended. In example #4 later in this section, this approach will be demonstrated.
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
156
PRELIMINARY
Freescale Semiconductor
Subject to Change