MC9S08DZ60 Datasheet, PDF (237/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Freescale’s Controller Area Network (S08MSCANV1)
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
1
AM1
0
0
AM0
0
Figure 12-21. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Field
7:0
AM[7:0]
Table 12-22. CANIDMR0–CANIDMR3 Register Field Descriptions
Description
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit (don’t care)
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
4
AM4
0
3
AM3
0
2
AM2
0
1
AM1
0
0
AM0
0
Figure 12-22. MSCAN Identifier Mask Registers (Second Bank) — CANIDMR4–CANIDMR7
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Field
7:0
AM[7:0]
Table 12-23. CANIDMR4–CANIDMR7 Register Field Descriptions
Description
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit (don’t care)
12.4 Programmer’s Model of Message Storage
The following section details the organization of the receive and transmit message buffers and the
associated control registers.
To simplify the programmer interface, the receive and transmit message buffers have the same outline.
Each message buffer allocates 16 bytes in the memory map containing a 13 byte data structure.
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
Freescale Semiconductor
PRELIMINARY
237
Subject to Change