MC9S08DZ60 Datasheet, PDF (213/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

11.5 Resets
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
Inter-Integrated Circuit (S08IICV2)
11.6 Interrupts
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in Table 11-10 occur, provided the IICIE bit
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. The
user can determine the interrupt type by reading the status register.
Table 11-10. Interrupt Summary
Interrupt Source
Complete 1-byte transfer
Match of received calling address
Arbitration Lost
Status
TCF
IAAS
ARBL
Flag
IICIF
IICIF
IICIF
Local Enable
IICIE
IICIE
IICIE
11.6.1 Byte Transfer Interrupt
The TCF (transfer complete flag) bit is set at the falling edge of the 9th clock to indicate the completion of
byte transfer.
11.6.2 Address Detect Interrupt
When the calling address matches the programmed slave address (IIC address register) or when the
GCAEN bit is set and a general call is received, the IAAS bit in the status register is set. The CPU is
interrupted, provided the IICIE is set. The CPU must check the SRW bit and set its Tx mode accordingly.
11.6.3 Arbitration Lost Interrupt
The IIC is a true multi-master bus that allows more than one master to be connected on it. If two or more
masters try to control the bus at the same time, the relative priority of the contending masters is determined
by a data arbitration procedure. The IIC module asserts this interrupt when it loses the data arbitration
process and the ARBL bit in the status register is set.
Arbitration is lost in the following circumstances:
• SDA sampled as a low when the master drives a high during an address or data transmit cycle.
• SDA sampled as a low when the master drives a high during the acknowledge bit of a data receive
cycle.
• A START cycle is attempted when the bus is busy.
• A repeated START cycle is requested in slave mode.
• A STOP condition is detected when the master did not request it.
This bit must be cleared by software by writing a 1 to it.
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
Freescale Semiconductor
PRELIMINARY
213
Subject to Change