MC9S08DZ60 Datasheet, PDF (150/396 Pages) Freescale Semiconductor, Inc – Microcontrollers

Multi-Purpose Clock Generator (S08MCGV1)
Table 8-6. MCGOUT Frequency Calculation Options
Clock Mode
PEE (PLL engaged external)
f_MCGOUT1
[(f_ext / R) * M] / B
PBE (PLL bypassed external)
f_ext / B
BLPI (Bypassed low power internal)
BLPE (Bypassed low power external)
f_int / B
f_ext / B
Note
f_ext / R must be in the range of 1
MHz to 2 MHz
f_ext / R must be in the range of 1
MHz to 2 MHz
1 _{R is the reference divider selected by the RDIV bits, B is the bus frequency divider selected by the BDIV bits,}
and M is the multiplier selected by the VDIV bits.
This section will include 3 mode switching examples using a 4 MHz external crystal. If using an external
clock source less than 1 MHz, the MCG should not be configured for any of the PLL modes (PEE and
PBE).
8.5.2.1 Example # 1: Moving from FEI to PEE Mode: External Crystal = 4 MHz,
Bus Frequency = 8 MHz
In this example, the MCG will move through the proper operational modes from FEI to PEE mode until
the 4 MHz crystal reference frequency is set to achieve a bus frequency of 8 MHz. Because the MCG is in
FEI mode out of reset, this example also shows how to initialize the MCG for PEE mode out of reset. First,
the code sequence will be described. Then a flowchart will be included which illustrates the sequence.
1. First, FEI must transition to FBE mode:
a) MCGC2 = 0x36 (%00110110)
– BDIV (bits 7 and 6) set to %00, or divide-by-1
– RANGE (bit 5) set to 1 because the frequency of 4 MHz is within the high frequency range
– HGO (bit 4) set to 1 to configure external oscillator for high gain operation
– EREFS (bit 2) set to 1, because a crystal is being used
– ERCLKEN (bit 1) set to 1 to ensure the external reference clock is active
b) Loop until OSCINIT (bit 1) in MCGSC is 1, indicating the crystal selected by the EREFS bit
has been initialized.
c) MCGC1 = 0xB8 (%10111000)
– CLKS (bits 7 and 6) set to %10 in order to select external reference clock as system clock
source
– RDIV (bits 5-3) set to %111, or divide-by-128 because 4 MHz / 128 = 31.25 kHz which is
in the 31.25 kHz to 39.0625 kHz range required by the FLL
– IREFS (bit 2) cleared to 0, selecting the external reference clock
d) Loop until IREFST (bit 4) in MCGSC is 0, indicating the external reference is the current
source for the reference clock
e) Loop until CLKST (bits 3 and 2) in MCGSC are %10, indicating that the external reference
clock is selected to feed MCGOUT
MC9S08DZ60 Series Data Sheet, Rev. 1 Draft E
150
PRELIMINARY
Freescale Semiconductor
Subject to Change