MC68HLC908QY4 Datasheet, PDF(86/182 Page) Motorola, Inc

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

MC68HLC908QY4 Datasheet, PDF (86/182 Pages) Motorola, Inc – Microcontrollers

◁

Low-Voltage Inhibit (LVI)

The LVI is enabled out of reset. The LVI module contains a bandgap reference circuit and comparator.

Clearing the LVI power disable bit (LVIPWRD) enables the LVI to monitor VDD voltage. Clearing the LVI

reset disable bit (LVIRSTD) enables the LVI module to generate a reset when VDD falls below a voltage,

VTRIPF or VDTRIPF. Setting the LVI enable in stop mode bit (LVISTOP) enables the LVI to operate in stop

mode. Setting the LVD or LVR trip point bit (LVDLVR) selects the LVD trip point voltage. The actual trip

thresholds are specified in 16.5 DC Electrical Characteristics. Either trip level can be used as a detect or

reset.

NOTE

After a power-on reset, the LVIâs default mode of operation is LVR trip

voltage. If a higher trip voltage is desired, the user must set the LVDLVR bit

to raise the trip point to the LVD voltage.

If the user requires the higher trip voltage and sets the LVDLVR bit after

power-on reset while the VDD supply is not above the VTRIPR for LVD

mode, the microcontroller unit (MCU) will immediately go into reset. The

next time the LVI releases the reset, the supply will be above the VTRIPR for

LVD mode.

Once an LVI reset occurs, the MCU remains in reset until VDD rises above a voltage, VTRIPR, which

causes the MCU to exit reset. See Chapter 13 System Integration Module (SIM) for the reset recovery

sequence.

The output of the comparator controls the state of the LVIOUT flag in the LVI status register (LVISR) and

can be used for polling LVI operation when the LVI reset is disabled.

10.3.1 Polled LVI Operation

In applications that can operate at VDD levels below the VTRIPF level, software can monitor VDD by polling

the LVIOUT bit. In the configuration register, the LVIPWRD bit must be cleared to enable the LVI module,

and the LVIRSTD bit must be set to disable LVI resets.

10.3.2 Forced Reset Operation

In applications that require VDD to remain above the VTRIPF level, enabling LVI resets allows the LVI

module to reset the MCU when VDD falls below the VTRIPF level. In the configuration register, the

LVIPWRD and LVIRSTD bits must be cleared to enable the LVI module and to enable LVI resets.

10.3.3 Voltage Hysteresis Protection

Once the LVI has triggered (by having VDD fall below VTRIPF), the LVI will maintain a reset condition until

VDD rises above the rising trip point voltage, VTRIPR. This prevents a condition in which the MCU is

continually entering and exiting reset if VDD is approximately equal to VTRIPF. VTRIPR is greater than

VTRIPF by the hysteresis voltage, VHYS.

10.3.4 LVI Trip Selection

The LVDLVR bit in the configuration register selects whether the LVI is configured for LVD (low voltage

detect) or LVR (low voltage reset) protection. The LVD trip voltage can be used as a low voltage warning.

The LVR trip voltage will commonly be configured as a reset condition since it is very close to the minimum

operating voltage of the device. The LVDLVR bit can be written to anytime so that battery applications

can make use of the LVI as both a warning indicator and to generate a system reset.

MC68HLC908QY/QT Family Data Sheet, Rev. 3

Freescale Semiconductor

▷