MC68HLC908QY4 Datasheet, PDF (27/182 Pages) Motorola, Inc – Microcontrollers

Input/Output (I/O) Section
Addr.
$001F
Register Name
Bit 7
6
5
4
3
2
1
Read:
Configuration Register 1
(CONFIG1)⁽¹⁾ Write:
See page 54. _Reset:
COPRS
0
LVISTOP LVIRSTD LVIPWRD LVDLVR
0
0
0
0⁽²⁾
SSREC
0
STOP
0
1. One-time writable register after each reset. Exceptions are LVDLVR and LVIRSTD bits.
2. LVDLVR reset to 0 by a power-on reset (POR) only.
Bit 0
COPD
0
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
Read:
TIM Status and Control
Register (TSC) Write:
See page 127. _Reset:
TIM Counter Register High ^Read:
(TCNTH) Write:
See page 129. _Reset:
TIM Counter Register Low ^Read:
(TCNTL) Write:
See page 129.
Reset:
Read:
TIM Counter Modulo
Register High (TMODH) Write:
See page 129. _Reset:
TIM Counter Modulo ^Read:
Register Low (TMODL) Write:
See page 129. _Reset:
TIM Channel 0 Status and ^Read:
Control Register (TSC0) Write:
See page 130.
Reset:
Read:
TIM Channel 0
Register High (TCH0H) Write:
See page 133. _Reset:
TIM Channel 0 ^Read:
Register Low (TCH0L) Write:
See page 133. _Reset:
TIM Channel 1 Status and ^Read:
Control Register (TSC1) Write:
See page 130.
Reset:
TOF
0
0
Bit 15
0
Bit 7
0
Bit 15
1
Bit 7
1
CH0F
0
0
Bit 15
Bit 7
CH1F
0
0
0
0
TOIE TSTOP
TRST
PS2
PS1
0
1
0
0
0
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
0
0
0
0
0
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
0
0
0
0
0
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
1
1
1
1
1
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
1
1
1
1
1
1
CH0IE MS0B MS0A ELS0B ELS0A TOV0
0
0
0
0
0
0
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Indeterminate after reset
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
CH1IE
Indeterminate after reset
0
MS1A ELS1B ELS1A TOV1
0
0
= Unimplemented
0
0
0
0
R = Reserved U = Unaffected
PS0
0
Bit 8
0
Bit 0
0
Bit 8
1
Bit 0
1
CH0MAX
0
Bit 8
Bit 0
CH1MAX
0
Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 6)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
27