MC68HLC908QY4 Datasheet, PDF (44/182 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
CH[4:0] — ADC Channel Select Bits
CH4, CH3, CH2, CH1, and CH0 form a 5-bit field which is used to select one of the four ADC channels.
The five select bits are detailed in Table 3-1. Care should be taken when using a port pin as both an
analog and a digital input simultaneously to prevent switching noise from corrupting the analog signal.
The ADC subsystem is turned off when the channel select bits are all set to 1. This feature allows for
reduced power consumption for the MCU when the ADC is not used. Reset sets all of these bits to a 1.
NOTE
Recovery from the disabled state requires one conversion cycle to stabilize.
Table 3-1. MUX Channel Select
CH4 CH3 CH2 CH1 CH0
0
0
0
0
0
ADC
Channel
AD0
Input Select
PTA0
0
0
0
0
1
AD1
PTA1
0
0
0
1
0
AD2
0
0
0
1
1
AD3
PTA4
PTA5
0
0
1
0
0
—
↓
↓
↓
↓
↓
—
1
1
0
1
0
—
Unused⁽¹⁾
1
1
0
1
1
—
Reserved
1
1
1
0
0
—
Unused
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
—
V_DDA(2)
—
V_SSA(2)
—
ADC power off
1. If any unused channels are selected, the resulting ADC conversion will be
unknown.
2. The voltage levels supplied from internal reference nodes, as specified in the
table, are used to verify the operation of the ADC converter both in
production test and for user applications.
3.7.2 ADC Data Register
One 8-bit result register is provided. This register is updated each time an ADC conversion completes.
Address: $003E
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 3-4. ADC Data Register (ADR)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
44
Freescale Semiconductor