MC68HLC908QY4 Datasheet, PDF (115/182 Pages) Motorola, Inc – Microcontrollers

Figure 13-15 and Figure 13-16 show the timing for wait recovery.
Low-Power Modes
ADDRESS BUS
$6E0B
$6E0C $00FF $00FE $00FD $00FC
DATA BUS $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt
Figure 13-15. Wait Recovery from Interrupt
ADDRESS BUS
$6E0B
32
CYCLES
32
CYCLES
RSTVCTH RSTVCTL
DATA BUS $A6 $A6
$A6
RST⁽¹⁾
BUSCLKX4
1. RST is only available if the RSTEN bit in the CONFIG1 register is set.
Figure 13-16. Wait Recovery from Internal Reset
13.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are disabled. An interrupt request from a
module can cause an exit from stop mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the oscillator signals (BUSCLKX2 and BUSCLKX4) in stop mode, stopping the CPU
and peripherals. Stop recovery time is selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal delay of 4096 BUSCLKX4 cycles
down to 32. This is ideal for the internal oscillator, RC oscillator, and external oscillator options which do
not require long start-up times from stop mode.
NOTE
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
115