MC68HLC908QY4 Datasheet, PDF (4/182 Pages) Motorola, Inc – Microcontrollers

Revision History
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date
August,
2003
October,
2003
January,
2004
July,
2005
Revision
Level
Description
Page
Number(s)
N/A
Initial release
N/A
Figure 2-2. Control, Status, and Data Registers Deleted unimplemented areas
from $FFB0–$FFBD and $FFC2–$FFCF as they are actually available. Also
26
corrected $FFBF designation from unimplemented to reserved.
Figure 6-1. COP Block Diagram — Reworked for clarity
57
6.3.2 STOP Instruction — Added subsection for STOP instruction
58
1.0
13.4.2 Active Resets from Internal Sources — Reworked notes for clarity.
115
15.3 Monitor Module (MON) — Clarified seventh bullet.
154
16.5 DC Electrical Characteristics — Corrected notes 4 and 5.
169
16.6 Control Timing — Updated values for RST input pulse width low and IRQ
interrupt pulse width low
170
Figure 2-2. Control, Status, and Data Registers — Corrected reset state for the
FLASH Block Protect Register at address location $FFBE and the Internal
30
2.0
Oscillator Trim Value at $FFC0.
Figure 2-5. FLASH Block Protect Register (FLBPR) — Restated reset state for
clarity.
37
Reformatted to meet current documentation standards
Chapter 7 Central Processor Unit (CPU) — In 7.7 Instruction Set Summary:
Reworked definitions for STOP instruction
Added WAIT instruction
3.0
13.8.1 SIM Reset Status Register — Clarified SRSR flag setting.
Throughout
70
71
117
14.9.1 TIM Status and Control Register — Added information to TSTOP note.
127
17.3 Package Dimensions — Updated package information.
163
MC68HLC908QY/QT Family Data Sheet, Rev. 3
4
Freescale Semiconductor