MC68HLC908QY4 Datasheet, PDF (112/182 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
The LDA opcode is prefetched by both the INT1 and INT2 return-from-interrupt (RTI) instructions.
However, in the case of the INT1 RTI prefetch, this is a redundant operation.
NOTE
To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.
13.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
13.6.2 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 13-3 summarizes the
interrupt sources and the interrupt status register flags that they set. The interrupt status registers can be
useful for debugging.
Table 13-3. Interrupt Sources
Priority
Source
Highest Reset
SWI instruction
IRQ pin
Timer channel 0 interrupt
Timer channel 1 interrupt
Timer overflow interrupt
Keyboard interrupt
Lowest ADC conversion complete interrupt
Flag
—
—
IRQF
CH0F
CH1F
TOF
KEYF
COCO
Mask⁽¹⁾
—
—
IMASK
CH0IE
CH1IE
TOIE
IMASKK
AIEN
INT
Register
Flag
—
—
IF1
IF3
IF4
IF5
IF14
IF15
Vector
Address
$FFFE–$FFFF
$FFFC–$FFFD
$FFFA–$FFFB
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFE0–$FFE1
$FFDE–$FFDF
1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI
instruction.
13.6.2.1 Interrupt Status Register 1
Address: $FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
IF5
IF4
IF3
0
IF1
0
0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 13-11. Interrupt Status Register 1 (INT1)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
112
Freescale Semiconductor