MC68HLC908QY4 Datasheet, PDF (45/182 Pages) Motorola, Inc – Microcontrollers

3.7.3 ADC Input Clock Register
This register selects the clock frequency for the ADC.
Input/Output Registers
Address: $003F
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
ADIV2 ADIV1 ADIV0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 3-5. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide ratio used by the ADC to generate
the internal ADC clock. Table 3-2 shows the available clock configurations. The ADC clock should be
set according to the MCU operating voltage. Lower operating voltages will require lower ADC clock
frequencies for best accuracy. The analog input level should remain stable for the entire conversion
time (maximum = 17 ADC clock cycles).
Table 3-2. ADC Clock Divide Ratio
ADIV2
ADIV1
0
0
0
0
0
1
0
1
1
X
X = don’t care
ADIV0
0
1
0
1
X
ADC Clock Rate
Bus clock ÷ 1
Bus clock ÷ 2
Bus clock ÷ 4
Bus clock ÷ 8
Bus clock ÷ 16
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
45