MC68HLC908QY4 Datasheet, PDF (55/182 Pages) Motorola, Inc – Microcontrollers

Functional Description
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module.
1 = LVI module power disabled
0 = LVI module power enabled
LVDLVR — Low Voltage Detect or Low Voltage Reset Mode Bit
LVDLVR selects the trip voltage of the LVI module. LVD trip voltage can be used as a low voltage
warning, while LVR will commonly be used as a reset condition. Unlike other CONFIG bits, LVDLVR
can be written multiple times after reset.
1 = LVI trip voltage level set to LVD trip voltage
0 = LVI trip voltage level set to LVR trip voltage
NOTE
The LVDLVR bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096
BUSCLKX4 cycle delay.
1 = Stop mode recovery after 32 BUSCLKX4 cycles
0 = Stop mode recovery after 4096 BUSCLKX4 cycles
NOTE
Exiting stop mode by an LVI reset will result in the long stop recovery.
The system stabilization time for power-on reset and long stop recovery (both 4096 BUSCLKX4
cycles) gives a delay longer than the LVI enable time for these startup scenarios. There is no period
where the MCU is not protected from a low-power condition. However, when using the short stop
recovery configuration option, the 32 BUSCLKX4 delay must be greater than the LVI’s turn on time to
avoid a period in startup where the LVI is not protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
55