MC68HLC908QY4 Datasheet, PDF (106/182 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
13.4.2 Active Resets from Internal Sources
The RST pin is initially setup as a general-purpose input after a POR. Setting the RSTEN bit in the
CONFIG2 register enables the pin for the reset function. This section assumes the RSTEN bit is set when
describing activity on the RST pin.
All internal reset sources actively pull the RST pin low for 32 BUSCLKX4 cycles to allow resetting of
external peripherals. The internal reset signal IRST continues to be asserted for an additional 32 cycles
(see Figure 13-4). An internal reset can be caused by an illegal address, illegal opcode, COP time out,
LVI, or POR (see Figure 13-5).
NOTE
For POR and LVI resets, the SIM cycles through 4096 BUSCLKX4 cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 13-4.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
IRST
RST
BUSCLKX4
ADDRESS
BUS
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 13-4. Internal Reset Timing
VECTOR HIGH
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
Figure 13-5. Sources of Internal Reset
Table 13-2. Reset Recovery Timing
Reset Recovery Type
POR/LVI
All others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
MC68HLC908QY/QT Family Data Sheet, Rev. 3
106
Freescale Semiconductor