MC68HLC908QY4 Datasheet, PDF (75/182 Pages) Motorola, Inc – Microcontrollers

IRQPUD
ACK
RESET
VECTOR
FETCH
DECODER
V_DD
INTERNAL
PULLUP
DEVICE
IRQ
V_DD
CLR
D
Q
CK
IRQ
LATCH
Functional Description
SYNCHRO-
NIZER
IMASK
IRQF
TO CPU FOR
BIL/BIH
INSTRUCTIONS
IRQ
INTERRUPT
REQUEST
MODE
HIGH
VOLTAGE
DETECT
Figure 8-2. IRQ Module Block Diagram
TO MODE
SELECT
LOGIC
8.3.1 MODE = 1
If the MODE bit is set, the IRQ pin is both falling edge sensitive and low level sensitive. With MODE set,
both of the following actions must occur to clear the IRQ interrupt request:
• Return of the IRQ pin to a high level. As long as the IRQ pin is low, the IRQ request remains active.
• IRQ vector fetch or software clear. An IRQ vector fetch generates an interrupt acknowledge signal
to clear the IRQ latch. Software generates the interrupt acknowledge signal by writing a 1 to ACK
in INTSCR. The ACK bit is useful in applications that poll the IRQ pin and require software to clear
the IRQ latch. Writing to ACK prior to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent transitions on the IRQ pin. A falling
edge that occurs after writing to ACK latches another interrupt request. If the IRQ mask bit, IMASK,
is clear, the CPU loads the program counter with the IRQ vector address.
The IRQ vector fetch or software clear and the return of the IRQ pin to a high level may occur in any order.
The interrupt request remains pending as long as the IRQ pin is low. A reset will clear the IRQ latch and
the MODE control bit, thereby clearing the interrupt even if the pin stays low.
Use the BIH or BIL instruction to read the logic level on the IRQ pin.
8.3.2 MODE = 0
If the MODE bit is clear, the IRQ pin is falling edge sensitive only. With MODE clear, an IRQ vector fetch
or software clear immediately clears the IRQ latch.
The IRQF bit in INTSCR can be read to check for pending interrupts. The IRQF bit is not affected by
IMASK, which makes it useful in applications where polling is preferred.
NOTE
When using the level-sensitive interrupt trigger, avoid false IRQ interrupts
by masking interrupt requests in the interrupt routine.
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
75