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MC68HLC908QY4 Datasheet, PDF (154/182 Pages) Motorola, Inc – Microcontrollers
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Electrical Specifications
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
Low-voltage inhibit reset, trip falling voltage (LVR)
VTRIPF
2.00
2.12
2.24
V
Low-voltage inhibit reset, trip rising voltage (LVR)
VTRIPR
2.04
2.18
2.30
V
Low-voltage inhibit reset/recover hysteresis
VHYS
—
60
—
mV
Low-voltage detect, trip falling voltage (LVD)
VDTRIPF
2.20
2.32
2.44
V
Low-voltage detect, trip rising voltage (LVD)
VDTRIPR
2.21
2.33
2.45
V
Low-voltage detect reset/recover hysteresis
VDHYS
—
10
—
mV
1. VDD = VDDMIN to VDDMAX, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.
2. Typical values reflect average measurements at VDD = 3.0 V, 25°C only.
3. Maximum is highest voltage that POR is guaranteed.
4. If minimum VDD is not reached before the internal POR reset is released, the LVI will hold the part in reset until minimum
VDD is reached.
5. RPU is measured at VDD = 3.0 V.
16.6 Control Timing
Characteristic(1)
Symbol
Min
Max
Internal operating frequency
fOP (fBus)
—
2
Internal clock period (1/fOP)
tcyc
500
—
RST input pulse width low
tRL
400
—
IRQ interrupt pulse width low (edge-triggered)
tILIH
400
—
IRQ interrupt pulse period
tILIL
Note(2)
—
1. VDD >= 2.2 V, VSS = 0 Vdc; timing shown with respect to 20% VDD and 70% VDD unless otherwise noted.
2. The minimum period is the number of cycles it takes to execute the interrupt service routine plus 1 tcyc.
Unit
MHz
ns
ns
ns
tcyc
tRL
RST
tILIL
tILIH
IRQ
Figure 16-1. RST and IRQ Timing
MC68HLC908QY/QT Family Data Sheet, Rev. 3
154
Freescale Semiconductor
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