MC68HLC908QY4 Datasheet, PDF (25/182 Pages) Motorola, Inc – Microcontrollers

Input/Output (I/O) Section
2.4 Input/Output (I/O) Section
Addresses $0000–$003F, shown in Figure 2-2, contain most of the control, status, and data registers.
Additional I/O registers have these addresses:
• $FE00 — Break status register, BSR
• $FE01 — Reset status register, SRSR
• $FE02 — Break auxiliary register, BRKAR
• $FE03 — Break flag control register, BFCR
• $FE04 — Interrupt status register 1, INT1
• $FE05 — Interrupt status register 2, INT2
• $FE06 — Interrupt status register 3, INT3
• $FE07 — Reserved
• $FE08 — FLASH control register, FLCR
• $FE09 — Break address register high, BRKH
• $FE0A — Break address register low, BRKL
• $FE0B — Break status and control register, BRKSCR
• $FE0C — LVI status register, LVISR
• $FE0D — Reserved
• $FFBE — FLASH block protect register, FLBPR
• $FFC0 — Internal OSC trim value — Optional
• $FFFF — COP control register, COPCTL
Addr.
$0000
$0001
$0002
Register Name
Port A Data Register ^Read:
(PTA) Write:
See page 98. _Reset:
Port B Data Register ^Read:
(PTB) Write:
See page 100.
Reset:
Unimplemented
Bit 7
R
PTB7
6
AWUL
PTB6
5
PTA5
PTB5
4
3
PTA4
PTA3
Unaffected by reset
PTB4
PTB3
Unaffected by reset
2
PTA2
PTB2
1
PTA1
PTB1
Bit 0
PTA0
PTB0
$0003
Unimplemented
$0004
Data Direction Register A ^Read:
R
(DDRA) Write:
See page 98. _Reset:
0
0
R
DDRA5 DDRA4 DDRA3
DDRA1
0
0
= Unimplemented
0
0
0
0
R = Reserved U = Unaffected
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 6)
DDRA0
0
MC68HLC908QY/QT Family Data Sheet, Rev. 3
Freescale Semiconductor
25