MC68HC705K1 Datasheet, PDF (80/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Multifunction Timer
8.5 COP Watchdog
Four counter stages at the end of the timer make up the mask-optional
computer operating properly (COP) watchdog. The COP watchdog is a
software error detection system that automatically times out and resets
the MCU if not cleared periodically by a program sequence. Writing a
logic 0 to bit 0 of the COP register clears the COP watchdog and
prevents a COP reset.
Address: $03F0
Bit 7
6
5
4
3
2
Read:
Write:
Reset: U
U
U
U
U
U
= Unimplemented
U = Unaffected
Figure 8-4. COP Register (COPR)
1
Bit 0
COPC
U
0
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $03F0
returns the read-only memory (ROM) data at that address.
The COP watchdog is active in the run, wait, and halt modes of
operation if the COPEN bit in the mask option register is set.
The STOP instruction disables the COP watchdog by clearing the
counter and turning off its clock source. In applications that depend
on the COP watchdog, the STOP instruction can be disabled by
programming the SWAIT bit to a logic 1 in the mask option register. In
applications that have wait cycles longer than the COP timeout
period, the COP watchdog can be disabled by not programming the
COPEN bit to a logic 1 in the mask option register.
NOTE: If the voltage on the IRQ/V_PP pin exceeds 2 × V_DD, the COP watchdog
turns off and remains off until the IRQ/V_PP voltage falls below 2 × V_DD.
Technical Data
Multifunction Timer
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MC68HC705K1 — Rev. 2.0