MC68HC705K1 Datasheet, PDF (55/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Resets
Reset States
5.3.5 Low-Voltage Reset
The low-voltage reset circuit generates a reset signal if the voltage on
the V_DD pin falls below 3.5 V (nominal). V_DD must be set at 5 V ±10%
while the low-voltage reset circuit is enabled.
Programming the LVRE bit to a logic 1 enables the low-voltage reset
function. When erased, the LVRE bit in the mask option register disables
the low-voltage reset circuit. See 9.6 Mask Option Register.
A low-voltage reset pulls the RESET pin low for as long as the
low-voltage condition exists.
The state of the low-voltage reset circuit is readable in the test register
at location $001F. Bit 1 of the test register is the low-voltage reset flag
(LVRF). Regardless of the LVRE bit in the mask option register, the
low-voltage reset circuit is active in all modes except stop mode.
5.4 Reset States
This subsection describes how resets initialize the MCU.
5.4.1 CPU
A reset has these effects on the central processor unit (CPU):
• Loads the stack pointer with $FF
• Sets the I bit in the condition code register, inhibiting interrupts
• Sets the IRQE bit in the interrupt status and control register
• Loads the program counter with the user-defined reset vector from
locations $03FE and $03FF
• Clears the stop latch, enabling the CPU clock
• Clears the wait latch, waking the CPU from the wait mode
MC68HC705K1 — Rev. 2.0
Resets
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Technical Data