MC68HC705K1 Datasheet, PDF (54/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Resets
Freescale Semiconductor, Inc.
5.3.3 Computer Operating Properly (COP) Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. (See 8.5 COP
Watchdog.) To clear the COP watchdog and prevent a COP reset, write
a logic 0 to bit 0 (COPC) of the COP register at location $03F0. The COP
register is a write-only register that returns the contents of a ROM
location when read.
Address: $03F0
Bit 7
6
5
4
3
2
Read:
Write:
Reset: U
U
U
U
U
U
= Unimplemented U = Unaffected
Figure 5-2. COP Register (COPR)
1
Bit 0
COPC
U
0
COPC — COP Clear Bit
COPC is a write-only bit. Periodically writing a logic 0 to COPC
prevents the COP watchdog from resetting the MCU. Writing a logic 1
has no effect. Reset clears the COPC bit.
5.3.4 Illegal Address Reset
An opcode fetch from an address that is not in the erasable,
programmable read-only memory (EPROM) (locations $0200–$03FF)
or the random-access memory (RAM) (locations $00E0–$00FF)
generates an illegal address reset. An illegal address reset pulls the
RESET pin low for one cycle of the internal clock.
Technical Data
Resets
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MC68HC705K1 — Rev. 2.0