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| MC68HC705K1 Datasheet, PDF (48/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit | |||
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Interrupts
Freescale Semiconductor, Inc.
Table 4-1 summarizes the reset and interrupt sources and vector
assignments.
Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
Local
Mask
Power-on logic
RESET pin
Reset
COP watchdog
None
Low voltage detect
Software
interrupt
(SWI)
External
interrupts
Illegal address logic
User code
IRQ/VPP pin
PA3 pin
PA2 pin
PA1 pin
None
IRQE bit
PA0 pin
Timer
interrupts
TOF bit
RTIF bit
TOFE bit
RTIE bit
1. COPEN enables the COP watchdog.
2. LVIE enables low-voltage resets.
3. PIRQ enables port A external interrupts.
Global
Mask
None
None
I bit
I bit
MOR
Control
Bit
None
None
COPEN(1)
LVIE(2)
None
Priority
(1 = Highest)
1
Vector
Address
$03FEâ$03FF
None
Same priority
as instruction
$03FCâ$03FD
None
PIRQ(3)
PIRQ3
PIRQ3
PIRQ3
2
$03FAâ$03FB
None
3
$03F8â$03F9
NOTE:
If more than one interrupt request is pending, the CPU fetches the vector
of the higher priority interrupt first. A higher priority interrupt does not
interrupt a lower priority interrupt service routine unless the lower priority
interrupt service routine clears the I bit.
Technical Data
Interrupts
For More Information On This Product,
Go to: www.freescale.com
MC68HC705K1 â Rev. 2.0
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