MC68HC705K1 Datasheet, PDF (67/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port A
7.4.4 Port A External Interrupts
Programming the PIRQ bit in the mask option register to a logic 1
enables the PA3–PA0 pins to serve as external interrupt pins in addition
to the IRQ/V_PP pin. The active interrupt state for the PA3–PA0 pins is a
logic 1 or a rising edge. The active interrupt state for the IRQ/V_PP pin is
a logic 0 or a falling edge. The state of the LEVEL bit in the mask option
register determines whether external interrupt inputs are edge-sensitive
only or both edge- and level-sensitive.
NOTE:
When testing for external interrupts, the branch if interrupt pin is high
(BIH) and branch if interrupt pin is low (BIL) instructions test the voltage
on the IRQ/V_PP pin, not the state of the internal IRQ signal. Therefore,
BIH and BIL cannot test the port A external interrupt pins.
7.4.5 Port A Logic
Figure 7-4 shows the port A I/O logic.
READ $0004
WRITE $0004
WRITE $0000
READ $0000
WRITE $0010
RESET
DATA DIRECTION
REGISTER A
BIT DDRAx
PORT A DATA
REGISTER
BIT PAx
PULLDOWN
REGISTER A
BIT PDIAx
MASK OPTION REGISTER ($0017)
EXTERNAL
INTERRUPT
REQUEST
(PINS PA3–PA0)
PAx
8-mA SINK
CAPABILITY
(PINS PA7–PA4)
100-µA
PULLDOWN
DEVICE
MC68HC705K1 — Rev. 2.0
Figure 7-4. Port A I/O Circuit
Parallel Input/Output (I/O)
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Technical Data