MC68HC705K1 Datasheet, PDF (69/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port B
is programmed to be an input, reading the port B data register returns
the logic state of the pin. Reset has no effect on port B data.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
0
0
0
0
0
PB1/
OSC3
PB0
Reset:
Unaffected by reset
= Unimplemented
Figure 7-5. Port B Data Register (PORTB)
PB1/OSC3 — Port B Data Bit 1/Oscillator Output Bit
This read/write data bit is software programmable. Data direction
of PB1 bit is under the control of the DDRB1 bit in data direction
register B.
When both the RC and PIN3 bits in the mask option register are set,
PB1/OSC3 can be used as an oscillator output in the 3-pin RC
oscillator configuration. Using PB1/OSC3 as an oscillator output
affects port B in these ways:
a. Bit PB1 can be used as a read/write storage location without
affecting the oscillator. Reset has no effect on bit PB1.
b. Bit DDRB1 in data direction register B can be used as a
read/write storage location without affecting the oscillator.
Reset clears DDRB1.
c. The PB1/OSC3 pulldown device is disabled, regardless of
the state of the SWPDI bit in the mask option register.
PB0 — Port B Data Bit 0
This read/write data bit is software programmable. Data direction of
PB0 is under the control of the DDRB0 bit in data direction register B.
Bits 7–2 — Not Used
Bits 7–2 always read as logic 0s. Writes to these bits have no effect.
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Technical Data