MC68HC705K1 Datasheet, PDF (45/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Interrupts
Interrupt Types
4.3.2.3 IRQ Status and Control Register
The IRQ status and control register (ISCR) contains an external interrupt
mask, an external interrupt flag, and a flag reset bit. Unused bits read as
logic 0s.
Address: $000A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
IRQF
IRQE
0
0
0
0
0
Write:
IRQR
Reset: 1
0
0
0
0
0
U
0
= Unimplemented U = Unaffected
Figure 4-2. IRQ Status and Control Register (ISCR)
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt processing enabled
0 = External interrupt processing disabled
IRQF — External Interrupt Request Flag
The IRQF bit is a clearable, read-only flag that is set when an external
interrupt request is pending. Reset clears the IRQF bit.
1 = Interrupt request pending
0 = No interrupt request pending
These conditions set the IRQF bit:
a. An external interrupt signal on the IRQ/V_PP pin
b. An external interrupt signal on pin PA3, PA2, PA1, or PA0
when PA3–PA0 are enabled to serve as external interrupt
sources
The CPU clears the IRQF bit when fetching the interrupt vector.
Writing to the IRQF bit has no effect. Writing a logic 1 to the IRQR bit
clears the IRQF bit.
MC68HC705K1 — Rev. 2.0
Interrupts
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Technical Data