MC68HC705K1 Datasheet, PDF (42/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Interrupts
Freescale Semiconductor, Inc.
Programming the LEVEL bit to a logic 0 selects the edge-sensitive-only
trigger option. When LEVEL = 0:
• A falling edge on the IRQ/V_PP pin latches an external interrupt
request.
• A subsequent interrupt request can be latched only after the
voltage level on the IRQ/V_PP pin returns to logic 1 and then falls
again to logic 0.
NOTE: If the IRQ/V_PP pin is not in use, connect it to the V_DD pin.
IRQ/V_PP
PA3
PA2
PA1
PA0
V_DD
IRQ
LATCH
R
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST
RST
IRQ VECTOR FETCH
MASK OPTION REGISTER
INTERNAL DATA BUS
IRQ STATUS/CONTROL REGISTER
Figure 4-1. External Interrupt Logic
Technical Data
Interrupts
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MC68HC705K1 — Rev. 2.0