MC68HC705K1 Datasheet, PDF (52/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Resets
Freescale Semiconductor, Inc.
5.3 Reset Types
A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address. These conditions produce a
reset:
• Initial power-up (power-on reset)
• A logic 0 applied to the RESET pin (external reset)
• Timeout of the computer operating properly (COP) watchdog
(COP reset)
• An opcode fetch from an address not in the memory map (illegal
address reset)
• V_DD voltage below nominal 3.5 volts (low-voltage reset)
5.3.1 Power-On Reset
A positive transition on the V_DD pin generates a power-on reset. The
power-on reset is strictly for power-up conditions and cannot be used to
detect drops in power supply voltage.
A 4064 t_CYC (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at
logic 0 at the end of 4064 t_CYC, the MCU remains in the reset condition
until the signal on the RESET pin goes to logic 1.
5.3.2 External Reset
A logic 0 applied to the RESET pin for one and one-half t_CYC generates
an external reset. A Schmitt trigger senses the logic level at the RESET
pin.
A COP reset or an illegal address reset pulls the RESET pin low for one
internal clock cycle. A low-voltage reset pulls the RESET pin low for as
long as the low-voltage condition exists.
Technical Data
Resets
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MC68HC705K1 — Rev. 2.0