MC68HC705K1 Datasheet, PDF (70/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
7.5.2 Data Direction Register B
The contents of data direction register B (DDRB) determine whether
each port B pin is an input or an output. Writing a logic 1 to a DDRB bit
enables the output buffer for the associated port B pin; a logic 0 disables
the output buffer. A reset initializes all DDRB bits to logic 0, configuring
all port B pins as inputs. Setting a DDRB bit to a logic 1 turns off the
pulldown device for that pin.
Address:
Read:
Write:
Reset:
$0005
Bit 7
6
5
4
3
2
1
0
0
0
0
0
0
DDRB1
0
0
0
0
0
0
0
= Unimplemented
Figure 7-6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB1 and DDRB0 — Data Direction Bits 1 and 0
These read/write bits control port B data direction.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Bit 7–2 — Not Used
Bits 7–2 always read as logic 0s. Writes to these bits have no effect.
NOTE: Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
7.5.3 Pulldown Register B
Programming the SWPDI bit in the mask option register to a logic 0
enables the port A and port B pulldown devices. The port B pulldown
devices sink approximately 100 µA and are under the control of the
PDIB1 and PDIB0 bits in pulldown register B (PDRB). Clearing PDIB1
and PDIB0 turns on the port B pulldown devices if they are configured
as inputs. A pulldown device can be turned on only when its pin is an
input. When SWPDI is a logic 0, reset initializes both port B pins as
inputs with pulldown devices turned on.
Technical Data
Parallel Input/Output (I/O)
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MC68HC705K1 — Rev. 2.0