MC68HC705K1 Datasheet, PDF (41/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Interrupts
Interrupt Types
4.3.2.1 IRQ/V_PP Pin
An interrupt signal on the IRQ/V_PP pin latches an external interrupt
request. After completing the current instruction, the CPU tests these
bits:
• IRQ latch
• IRQE bit in the interrupt status and control register
• I bit in the condition code register
If both the IRQ latch and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request. Figure 4-1 shows the logic for
external interrupts.
The IRQ/V_PP pin is negative edge-triggered only or negative edge- and
low-level-triggered, depending on the state of the LEVEL bit in the mask
option register (MOR). See 9.6 Mask Option Register.
Programming the LEVEL bit to a logic 1 selects the edge- and
level-sensitive trigger option. When LEVEL = 1:
• A falling edge or a low level on the IRQ/V_PP pin latches an external
interrupt request.
• As long as the IRQ/V_PP is low, an external interrupt request is
present, and the CPU continues to execute the interrupt service
routine. The edge- and level-sensitive trigger option allows
connection to the IRQ/V_PP pin of multiple wired-OR interrupt
sources.
MC68HC705K1 — Rev. 2.0
Interrupts
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Technical Data