MC68HC705K1 Datasheet, PDF (73/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port B
When a port B pin is programmed as an output, reading the port bit reads
the value of the data latch and not the voltage on the pin itself. When a
port B pin is programmed as an input, reading the port bit reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its DDR bit. Table 7-2 summarizes the operation of the
PB0 pin.
Programming the RC and PIN3 bits to logic 1 disables the PB1/OSC3
output buffer and pulldown device. The PB1/OSC3 bit becomes an
output from the 3-pin RC oscillator. The DDRB1 and PB1 bits are
available as read/write storage locations; reset clears DDRB1 but does
not affect PB1. Table 7-3 summarizes the operation of the PB1/OSC3
pin.
Control Bits
SWPDI
1
1
PDIB0
X⁽¹⁾
X
DDRB0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
1. X = Don’t care
2. U = Undefined
Table 7-2. PB0 Pin Functions
PB0
Pin Mode
Input, hi-z
Output
Input,
pulldown on
Output
Input, hi-z
Output
Accesses
to PDRB
Read Write
U⁽²⁾
PDIB0
U
PDIB0
U
PDIB0
U
PDIB0
U
PDIB0
U
PDIB0
Accesses
to DDRB
Read/Write
DDRB0
DDRB0
DDRB0
DDRB0
DDRB0
DDRB0
Accesses
to PORTB
Read Write
Pin
PB0
PB0
PB0
Pin
PB0
PB0
PB0
Pin
PB0
PB0
PB0
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Technical Data