MC68HC705K1 Datasheet, PDF (59/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Low-Power Modes
Halt Mode
These conditions restart the CPU clock and bring the MCU out of wait
mode:
• An external interrupt signal on the IRQ/V_PP pin — A high-to-low
transition on the IRQ/V_PP pin loads the program counter with the
contents of locations $03FA and $03FB.
• An external interrupt signal on a port A external interrupt pin — If
the PIRQ bit in the mask option register is programmed to a
logic 1, a low-to-high transition on a PA3–PA0 pin loads the
program counter with the contents of locations $03FA and $03FB.
• A timer interrupt — A timer overflow or a real-time interrupt request
loads the program counter with the contents of locations $03F8
and $03F9.
• A COP watchdog reset — A timeout of the COP watchdog resets
the MCU and loads the program counter with the contents of
locations $03FE and $03FF. Software can enable real-time
interrupts so that the MCU can periodically exit wait mode to reset
the COP watchdog.
• External reset — A logic 0 on the RESET pin resets the MCU and
loads the program counter with the contents of locations $03FE
and $03FF.
6.5 Halt Mode
The STOP instruction puts the MCU in halt mode if the SWAIT bit in the
mask option register is programmed to a logic 1. Halt mode is identical
to wait mode, except that a recovery delay of 1–4064 internal clock
cycles occurs when the MCU exits halt mode. When the SWAIT bit is set,
the COP watchdog cannot be inadvertently turned off by a STOP
instruction.
Figure 6-1 shows the sequence of events in stop, wait, and halt modes.
MC68HC705K1 — Rev. 2.0
Low-Power Modes
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Technical Data