MC68HC705K1 Datasheet, PDF (43/140 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Interrupts
Interrupt Types
4.3.2.2 PA3–PA0 Pins
Programming the PIRQ bit in the mask option register to a logic 1
enables pins PA3–PA0 to serve as additional external interrupt sources.
See 9.6 Mask Option Register. An interrupt signal on a PA3–PA0 pin
latches an external interrupt request. After completing the current
instruction, the CPU tests these bits:
• IRQ latch
• IRQE bit in the IRQ status and control register
• I bit in the condition code register.
If both the IRQ latch and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
The PA3–PA0 pins are edge-triggered only or both edge- and
level-triggered, depending on the state of the LEVEL bit in the MOR.
Programming the LEVEL bit to a logic 1 selects the edge- and
level-sensitive trigger option. When LEVEL = 1:
• A rising edge or a high level on a PA3–PA0 pin latches an external
interrupt request if and only if all other PA3–PA0 pins are low and
the IRQ/V_PP pin is high.
• A falling edge or a low level on the IRQ/V_PP pin latches an external
interrupt request if and only if all of the PA3–PA0 pins are low.
• As long as any PA3–PA0 pin is high or the IRQ/V_PP pin is low, an
external interrupt request is present, and the CPU continues to
execute the interrupt service routine.
MC68HC705K1 — Rev. 2.0
Interrupts
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