SGTL5000XNAA3 Datasheet, PDF (8/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

SGTL5000
DATASHEET
Table 7. SPI Bus Timing
Symbol
Parameter
Min
Tspidh
SPI data input hold time
10
Tspiclkl
SPI CTRL_CLK low time
???
Tspiclkh SPI CTRL_CLK high time
???
Tccs
SPI clock to chip select
60
Tcsc
SPI chip select to clock
20
Tcsl
SPI chip select low
20
Tcsh
SPI chip select high
20
Typical
Max Unit
nS
nS
nS
nS
nS
nS
nS
CTRL_AD0_CS
CTRL_CLK
Tcsl
Tcsh
1/Fspi_clk
Tspiclkh Tspiclkl
Tccs
Tcsc
Tspidsu
Tspidh
CTRL_DATA
Figure 3. SPI Timing
1.3.4.
I2S
The following are the specifications and timing for I2S port. The timing applies to all
formats.
Table 1-1.
Symbol
Parameter
Min
Typical
Max
Unit
Flrclk
Frequency of I2S_LRCLK
???
96
kHz
Fsclk
Frequency of I2S_SCLK
32*Flrclk,
kHz
64*Flrclk
Ti2s_d
I2S delay
10
ns
Ti2s_s
I2S setup time
10
ns
8
SGTL5000 EA2 DS-0-3