SGTL5000XNAA3 Datasheet, PDF (46/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

SGTL5000
DATASHEET
// to 75mA
Write CHIP_SHORT_CTRL
0x1106
// Enable Zero-cross detect if needed for HP_OUT (bit 5) and ADC (bit 1)
Write CHIP_ANA_CTRL
0x0133
//----------------Power up Inputs/Outputs/Digital Blocks-------------
// Power up LINEOUT, HP, ADC, DAC
Write CHIP_ANA_POWER
0x6AFF
// Power up desired digital blocks
// I2S_IN (bit 0), I2S_OUT (bit 1), DAP (bit 4), DAC (bit 5),
// ADC (bit 6) are powered on
Write CHIP_DIG_POWER
0x0073
//--------------------Set LINEOUT Volume Level-----------------------
// Set the LINEOUT volume level based on voltage reference (VAG)
// values using this formula
// Value = (int)(40*log(VAG_VAL/LO_VAGCNTRL) + 15)
// Assuming VAG_VAL and LO_VAGCNTRL is set to 0.9V and 1.65V respectively, the
// left LO vol (bits 12:8) and right LO volume (bits 4:0) value should be set
// to 5
Write CHIP_LINE_OUT_VOL
0x0505
6.2.1.2. System MCLK and Sample Clock
// Configure SYS_FS clock to 48kHz
// Configure MCLK_FREQ to 256*Fs
Modify CHIP_CLK_CTRL->SYS_FS 0x0002 // bits 3:2
Modify CHIP_CLK_CTRL->MCLK_FREQ 0x0000 // bits 1:0
// Configure the I2S clocks in master mode
// NOTE: I2S LRCLK is same as the system sample clock
Modify CHIP_I2S_CTRL->MS 0x0001 // bit 7
6.2.2.
PLL Configuration
These programming steps are needed only when the PLL is used. Please refer to
section 5.4.2 for details on when to use the PLL.
To avoid any pops/clicks, the outputs should be muted during these chip configura-
tion steps. Refer to section 6.2.6 for volume and mute control.
// Power up the PLL
Modify CHIP_ANA_POWER->PLL_POWERUP 0x0001 // bit 10
Modify CHIP_ANA_POWER->VCOAMP_POWERUP 0x0001 // bit 8
// NOTE: This step is required only when the external SYS_MCLK
// is above 17MHz. In this case the external SYS_MCLK clock
// must be divided by 2
Modify CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 0x0001 // bit 3
Sys_MCLK_Input_Freq = Sys_MCLK_Input_Freq/2;
// PLL output frequency is different based on the sample clock
// rate used.
if (Sys_Fs_Rate == 44.1kHz)
PLL_Output_Freq = 180.6336MHz
else
PLL_Output_Freq = 196.608MHz
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SGTL5000 EA2 DS-0-3