SGTL5000XNAA3 Datasheet, PDF (25/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

DATASHEET
SGTL5000
5
4
3
32QFN Typical Connection Diagram
D
2
VDDD
C?
0.1uF
U?
1
CTRL_CLK
6,7
CTRL_DATA 6,7
D
I2S_DIN
7
I2S_DOUT
7
I2S_SCLK
7
I2S_LRCLK 7
SYS_MCLK
C
J?
2
3
4
5
1
Audio Jack
VDDA
1
2
3
4
5
6
7
8
GND
HP_R
GND
HP_VGND
VDDA
HP_L
AGND
NC
I2S_SCLK
I2S_LRCLK
NC
SYS_MCLK
VDDIO
NC
CPFILT
NC
24
23
22
21
20
19
18
17
VDDIO
C
C?
0.1uF
GND ^PAD
C?
0.1uF
Notes:
1. The above circuit shows VDDD (pin 30) being derived
SGTL5000_32QFN
C?
Solder Pad to GND
C?
0.1uF
X?
1
2
internally. For lowest power operation VDDD can be
MIC
B driven from an external 1.2V supply with .1uF of
decoupling to ground.
0.1uF
C? 1uF
5 LINE_OUT_R
C?
R? 2.2k
B
1uF
2. If both VDDIO and VDDA are below 3V, the CPFILT pin
(pin 17) must be connected to a .1uF CAP to ground. If
5 LINE_OUT_L
C? 1uF
C? 1uF
either is above 3V, this CAP is not needed.
LINE_IN_L
4
3. The above shows I2C implementation as CTRL_MODE
C? 1uF
(pin 32) is tied to ground). In addition, address 0 of
LINE_IN_R 4
the I2C address is 0 as CTRL_ADR0_CS (pin 31) is tied
to ground.
4. AGND (pin 7) should be "star" connected to the jack
grounds for line in and line out and the ground side of
the capacitor tied to VAG. This node should via to the
ground plane (or connected to ground) at a single
A _point.
A
5
4
3
2
1
SGTL5000 EA2 DS-0-3
25