SGTL5000XNAA3 Datasheet, PDF (31/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

DATASHEET
SGTL5000
To configure a route, the CHIP_SSS_CTRL register is used. Each output from the
source select switch has its own register field that is used to select what input is
routed to that output.
For example, to route the I2S digital input through the DAP and then out to the DAC
(headphone) outputs write SSS_CTRL->DAP_SELECT to 0x1 (selects I2S_IN) and
SSS_CTRL->DAC_SELECT to 0x3 (selects DAP output).
5.6. Analog Input Block
The analog input block contains a stereo line input and a microphone input with mic
bias (in the 32QFN package). Either input can be routed to the ADC. The line input
can also configured to bypass the CODEC and be routed the analog input directly to
the headphone output.
5.6.1.
Line Inputs
One stereo line input is provided for connection to line sources such as an FM radio
or MP3 input.
The source should be connected to the left and right line inputs through series cou-
pling capacitors. The suggested value is shown in the typical connection diagram in
section 4.
As detailed in section 5.6.3, the line input can be routed to the ADC.
The line input can also be routed to the headphone output by writing
CHIP_ANA_CTRL->SELECT_HP. This selection bypasses the ADC and audio
switch and routes the line input directly to the headphone output to enable a very
low power pass through.
5.6.2.
Microphone Input
One mono microphone input is provided for uses such as voice recording.
Mic bias is provided in the 32QFN package. The mic bias is can be programmed
with the CHIP_MIC_CTRL->BIAS_VOLT registor field. Values from 1.25V to 3.00V
are supported in 0.25V steps. Mic bias should be set less than 200mV from VDDA,
e.g. with VDDA at 1.70V, Mic bias should be set no greater than 1.50V.
The microphone should be connected through a series coupling capacitor. The sug-
gested value is shown in the typical connection diagram.
The microphone has programmable gain through the CHIP_MIC_CTRL->GAIN reg-
ister field. Values of 0dB, +20dB, +30dB and +40dB are available.
5.6.3.
ADC
The SGTL5000 contains an ADC who takes its input from either the line input or a
microphone. The register field CHIP_ANA_CTRL->SELECT_ADC controls this
selection. The output of the ADC feeds the audio switch.
The ADC has its own analog gain stage that provides 0 to +22.5dB of gain in 1.5dB
steps. A bit is available that shifts this range down by 6dB to effectively provide
-6dB to +16.5dB of gain. The ADC gain is controlled in the CHIP_ANA_ADC_CTRL
register.
SGTL5000 EA2 DS-0-3
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