SGTL5000XNAA3 Datasheet, PDF (33/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

DATASHEET
SGTL5000
The lineout volume is intended as maximum output level adjustment. It is intended
to be used to set the maximum output swing. It does not have the range of a typical
volume control and does not have a zero cross detect (ZCD). However the dac digi-
tal volume could be used if volume control is desired
5.8. Digital Input & Output
One I2S (Digital Audio) Port is provided which supports the following formats: I2S,
Left Justified, Right Justified and PCM mode.
5.8.1.
I2S, Left Justified and Right Justified Modes
I2S, Left Justified and Right Justified modes are stereo interface formats. The
I2S_SCLK frequency, I2S_SCLK polarity, I2S_DIN/DOUT data length, and
I2S_LRCLK polarity can all be change through the CHIP_I2S_CTRL register. For
I2S, Left Justified and Right Justified formats the left subframe should always be
presented first regardless of the CHIP_I2S_CTRL->LRPOL setting.
The I2S_LRCLK and I2S_SCLK can be programmed as master (driven to an exter-
nal target) or slave (driven from an external source). When the clocks are in slave
mode, they must be synchronous to SYS_MCLK. For this reason the SGTL5000
can only operate in synchronous mode (see section 5.4) while in I2S slave mode.
In master mode, the clocks will be synchronous to SYS_MCLK or the output of the
PLL when the part is running in asynchronous mode.
Figure 12 shows functional examples of different common digital interface formats
and their associated register settings.
SGTL5000 EA2 DS-0-3
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