SGTL5000XNAA3 Datasheet, PDF (68/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

SGTL5000
DATASHEET
BITS
FIELD
RW RESET
DEFINITION
1 ADC_POWERUP RW 0x0
Power up the ADCs
0x0 = Power down
0x1 = Power up
0 LINEOUT_POWE RW 0x0
RUP
Power up the lineout amplifiers
0x0 = Power down
0x1 = Power up
7.0.0.18. CHIP_PLL_CTRL
0x0032
This register may only be changed after reset, and before PLL_POWERUP is set.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BITS
15:11
FIELD
INT_DIVISOR
RW RESET
DEFINITION
RW 0xA
This is the integer portion of the PLL divisor. To determine the
value of this field, use the following calculation:
INT_DIVISOR = FLOOR(PLL_OUTPUT_FREQ/
INPUT_FREQ)
PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate
= 44.1 KHz
else
PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate
!= 44.1 KHz
10:0 FRAC_DIVISOR RW 0x0
INPUT_FREQ = Frequency of the external MCLK provided if
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x0
else
INPUT_FREQ = (Frequency of the external MCLK provided/2)
If CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1
This is the fractional portion of the PLL divisor. To determine
the value of this field, use the following calculation:
FRAC_DIVISOR = ((PLL_OUTPUT_FREQ/INPUT_FREQ) -
INT_DIVISOR)*2048
PLL_OUTPUT_FREQ = 180.6336 MHz if System sample rate
= 44.1 KHz
else
PLL_OUTPUT_FREQ = 196.608 MHz if System sample rate
!= 44.1 KHz
INPUT_FREQ = Frequency of the external MCLK provided if
CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x0
else
INPUT_FREQ = (Frequency of the external MCLK provided/2)
If CHIP_CLK_TOP_CTRL->INPUT_FREQ_DIV2 = 0x1
68
SGTL5000 EA2 DS-0-3