SGTL5000XNAA3 Datasheet, PDF (58/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

SGTL5000
DATASHEET
BITS
FIELD
RW RESET
DEFINITION
15:14
RSVD
RO 0x0 Reserved
13 VOL_BUSY_DAC RO 0x0
_RIGHT
Volume Busy DAC Right
0x0 = Ready
0x1 = Busy - This indicates the channel has not reached its
programmed volume/mute level
12 VOL_BUSY_DAC RO 0x0
_LEFT
Volume Busy DAC Left
0x0 = Ready
0x1 = Busy - This indicates the channel has not reached its
programmed volume/mute level
11:10
RSVD
RO 0x0 Reserved
9 VOL_RAMP_EN RW 0x1
Volume Ramp Enable
0x0 = Disables volume ramp. New volume settings will take
immediate effect without a ramp
0x1 = Enables volume ramp
This field affects DAC_VOL. The volume ramp effects both
volume settings and mute. When set to 1 a soft mute is
enabled.
8 VOL_EXPO_RAM RW 0x0
P
Exponential Volume Ramp Enable
0x0 = Linear ramp over top 4 volume octaves
0x1 = Exponential ramp over full volume range
This bit only takes effect if VOL_RAMP_EN is 1.
7:4
RSVD
RW 0x0 Reserved
3 DAC_MUTE_RIG RW 0x1
HT
DAC Right Mute
0x0 = Unmute
0x1 = Muted
If VOL_RAMP_EN = 1, this is a soft mute.
2 DAC_MUTE_LEF RW 0x1
T
DAC Left Mute
0x0 = Unmute
0x1 = Muted
If VOL_RAMP_EN = 1, this is a soft mute.
1 ADC_HPF_FREE RW 0x0
ZE
ADC High Pass Filter Freeze
0x0 = Normal operation
0x1 = Freeze the ADC high-pass filter offset register. The
offset will continue to be subtracted from the ADC data
stream.
0 ADC_HPF_BYPA RW 0x0
SS
ADC High Pass Filter Bypass
0x0 = Normal operation
0x1 = Bypassed and offset not updated
7.0.0.7. CHIP_DAC_VOL
0x0010
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
58
SGTL5000 EA2 DS-0-3