SGTL5000XNAA3 Datasheet, PDF (34/84 Pages) Freescale Semiconductor, Inc – Low Power Stereo Codec with Headphone Amp

SGTL5000
DATASHEET
I2S Format (n = bit length)
CHIP_I2S0_CTRL field values:
(SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 0; LRPOL = 0)
I2S_LRCLK
I2S_SCLK
I2S_DIN, DOUT
Ln L(n-1)
L01 L00
Rn R(n-1)
R01 R00
Ln
Left Justified Format (n = bit length)
CHIP_I2S0_CTRL field values:
(SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 0; LRALIGN = 1; LRPOL = 0)
I2S_LRCLK
I2S_SCLK
I2S_DIN, DOUT
Ln L(n-1)
L1 L0
Rn R(n-1)
R1 R0
Ln L(n-1)
Right Justified Format (n = bit length)
CHIP_I2S0_CTRL field values:
SCLKFREQ = 0; SCLK_INV = 0; DLEN = 1; I2S_MODE = 1; LRALIGN = 1; LRPOL = 0)
I2S_LRCLK
I2S_SCLK
I2S_DIN, DOUT
Ln L(n-1)
L0
Rn R(n-1)
R0
Figure 12. I2S Port Supported Formats
5.8.2.
PCM Mode
The I2S port can also be configured into a PCM mode (also known as DSP mode).
This mode is provided to allow connectivity to to external devices such as Bluetooth
modules. PCM mode differs from other interface formats presented in section 5.8.1
in that the frame clock (I2S_LRCLK) does not represent a different channel when
high or low, but is a bit-wide pulse that marks the start of a frame. Data is aligned
such that the left channel data is immediately followed by right channel data. Zero
padding is filled in for the remaining bits. The data and frame clock may be config-
ured to clock in on the rising or falling edge of Bit Clock.
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SGTL5000 EA2 DS-0-3